View CS4270-CZZ_1003100.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 24-bit, 192 khz stereo audio codec d/a features ? high performance ? 105 db dynamic range ? -95 db thd+n ? selectable serial audio interface formats ? left-justified up to 24-bit ? i2s up to 24-bit ? right-justified 16-, and 24-bit ? control output for external muting ? on-chip digital de-emphasis ? popguard technology ? multi-bit ? conversion ? digital volume control a/d features ? high performance ? 105 db dynamic range ? -95 db thd+n ? multi-bit delta sigma conversion ? high-pass filter to remove dc offsets ? selectable serial audio interface formats ? left-justified up to 24-bit ? i2s up to 24-bit system features ? direct interface with logic levels 1.8 v to 5 v ? internal digital loopback ? stand-alone or control port functionality ? single-ended analog architecture ? supports all audio sample rates from 4 khz to 216 khz control port supply 1.8 v to 5 v register/hardware configuration internal voltage reference reset serial interface level translator digital supply 3.3 v to 5 v hardware mode or i 2 c/spi software mode control data analog supply 3.3 v to 5 v single-ended outputs 2 pcm serial audio input volume controls digital filters switch-cap dac and analog filters multi-bit ? modulators external mute control mute signals 2 2 2 2 switch-cap adc single-ended inputs digital filters high-pass filter pcm serial audio output may '05 ds686a1 cs4270
2 ds686a1 cs4270 stand-alone mode feature set ? system features ? serial audio port master or slave operation ? single, double, or quad-speed operation ? d/a features ? auto-mute on static samples ? 44.1 khz 50/15 s de-emphasis available ? selectable serial audio interface formats ? left-justified up to 24-bit ? i2s up to 24-bit ? a/d features ? high-pass filter ? selectable serial audio interface formats ? left-justified up to 24-bit ? i2s up to 24-bit software mode feature set ? system features ? serial audio port master or slave operation ? internal digital loopback available ? d/a features ? selectable auto-mute ? 44.1-khz de-emphasis filters ? configurable muting controls ? volume control ? selectable serial audio interface formats ? left-justified up to 24-bit ? i2s up to 24-bit ? right justified 16, and 24-bit ? a/d features ? selectable high-pass filter or dc offset calibration ? selectable serial audio interface formats ? left-justified up to 24-bit ? i2s up to 24-bit general description the cs4270 is a high-performance, integrated audio codec. the cs4270 performs stereo analog-to-digital (a/d) and digital-to-analog (d/a) conversion of up to 24-bit serial values at sample rates up to 216 khz. standard 50/15 s de-emphasis is available for sam- pling rates of 44.1 khz for co mpatibility with digital audio programs mastered using the 50/15 s pre-emphasis technique. integrated level translators allow easy interfacing be- tween the cs4270 and other devices operating over a wide range of logic levels. independently addressable high-pass filters are avail- able for the right and left channel of the a/d. this allows the a/d to be used in a wide variety of applications where one audio channel and one dc measurement channel is desired. the cs4270?s wide dynamic range, negligible distor- tion, and low noise make it id eal for applications such as dvd-recorders, digi tal televisions, se t top boxes, ef- fects processors, and automotive audio systems. ordering information product description package pb-free grade temp range container order # cs4270 24-bit 192 khz stereo audio codec 24-tssop yes commercial -10 to +85 c rail CS4270-CZZ tape & reel CS4270-CZZr cs4270 24-bit 192 khz stereo audio codec 24-tssop yes commercial -40 to +85 c rail cs4270-dzz tape & reel cs4270-dzzr cdb4270 cs4270 evaluation board - - - - - cdb4270
ds686a1 3 cs4270 table of contents 1. pin descriptions - software mode ............................................................................. 6 2. pin descriptions - stand-alone mode ....................................................................... 7 3. characteristics and specifications ........................................................................ 8 specified operating conditions . .............. ................ ............. ............. ............. ........... 8 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 8 thermal characteristics.............................................................................................. 8 dac analog characteristics (CS4270-CZZ)............................................................... 9 dac analog characteristics (cs4270-dzz)............................................................... 9 dac combined interpolation & on-chip analog filter response................ 11 adc analog characteristics (CS4270-CZZ)............................................................. 12 adc analog characteristics (cs4270-dzz)............................................................. 13 adc analog characteristics - all modes ............................................................. 14 adc digital filter characteristics ........................................................................ 14 dc electrical characteristics ................................................................................ 15 digital characteristics............................................................................................... 16 switching characteristics - serial audio port................................................. 16 switching characteristics - i2c mode control port....................................... 19 switching characteristics - spi control port.................................................. 20 4. typical connection diagram ..................................................................................... 21 5. applications .............................................................................................................. ....... 22 5.1 stand-alone mode .......................................................................................................... .22 5.1.1 recommended power-up sequence .... ............................................................. 22 5.1.2 master/slave mode ............................. ................................................................ 22 5.1.3 system clocking ................................................................................................. 22 5.1.4 clock ratio selection .......................................................................................... 23 5.1.5 interpolation filter .............................................................................................. 23 5.1.6 high-pass filter .................................................................................................. 23 5.1.7 mode selection & de-emphasis ......................................................................... 24 5.1.8 serial audio interface format select ion ............................................................. 24 5.2 control port mode ......................................................................................................... .. 24 5.2.1 recommended power-up sequence - acce ss to control port mode ................ 24 5.2.2 master / slave mode se lection ........................................................................... 24 5.2.3 system clocking ................................................................................................. 25 5.2.4 clock ratio selection .......................................................................................... 25 5.2.5 internal digital loopback .................................................................................... 26 5.2.6 auto-mute ........................................................................................................... 26 5.2.7 high-pass filter and dc offset calibra tion ........................................................ 26 5.2.8 de-emphasis ...................................................................................................... 27 5.2.9 oversampling modes .......................................................................................... 27 5.3 de-emphasis filter ........................................................................................................ .. 27 5.4 analog connections ........................................................................................................ 28 5.4.1 input connections ............................................................................................... 28 5.4.2 output connections ............................................................................................ 29 5.5 mute control .............................................................................................................. ...... 29 5.6 synchronization of multiple devices ................................................................................ 30 5.7 grounding and power supply decoupling .... ................................................................... 30 6. control port interface .............................................................................................. 31 6.1 spi? mode ................................................................................................................. .... 31 6.2 i2c mode .................................................................................................................. ........ 32 7. register quick reference .......................................................................................... 33 8. register description .................................................................................................... 34 8.1 chip id - address 01h ..................................................................................................... 34
4 ds686a1 cs4270 8.2 power control - address 02h .......................................................................................... 34 8.2.1 freeze (bit 7) ...................................................................................................... 34 8.2.2 pdn_adc (bit 5) ................................................................................................ 34 8.2.3 pdn_dac (bit 1) ................................................................................................ 34 8.2.4 power down (bit 0) ............................................................................................. 34 8.3 mode control - address 03h ............................................................................................ 35 8.3.1 adc functional mode & master / slave mode (bits 5:4) .................................... 35 8.3.2 ratio select (bits 3:1) ......................................................................................... 35 8.3.3 popguard disable (bit 0) .................................................................................... 35 8.4 adc and dac control - address 04h ............................................................................. 35 8.4.1 adc hpf freeze a (bit 7) ............... ................................................................... 35 8.4.2 adc hpf freeze b (bit 6) ............... ................................................................... 36 8.4.3 digital loopback (bit 5) ....................................................................................... 36 8.4.4 dac digital interface format (bits 4:3) ............................................................... 36 8.4.5 adc digital interface format (bit 0) ................................................................... 36 8.5 transition control - address 05h ..................................................................................... 37 8.5.1 dac single volume (bit 7) ............... ................................................................... 37 8.5.2 soft ramp or zero cross enable (bits 6:5) ........................................................ 37 8.5.3 invert signal polarity (bits 4:1) ...... ...................................................................... 37 8.5.4 de-emphasis control (bit 0) ............................................................................... 38 8.6 mute control - address 06h ............................................................................................. 38 8.6.1 auto-mute (bit 5) ................................................................................................. 38 8.6.2 adc channel a & b mute (bits 4:3) ................................................................... 38 8.6.3 mute polarity (bit 2) ............................................................................................ 38 8.6.4 dac channel a & b mute (bits 1:0) ................................................................... 38 8.7 dac channel a volume control - address 07h .............................................................. 39 8.8 dac channel b volume control - address 08h .............................................................. 39 10. package dimensions .................................................................................................... 41 11. appendix ............. ................ ................ ................. ................ ................ .............. ........... 42 12. revision history ......................................................................................................... ... 48 list of figures figure 1. output test load .................................................................................................... ................... 10 figure 2. maximum loading ..................................................................................................... ................. 10 figure 3. master mode serial audio port timing ................................................................................ ...... 17 figure 4. slave mode serial audio port timing ................................................................................. ....... 17 figure 5. format 0, left justified up to 24-bit da ta .......................................................................... ........ 18 figure 6. format 1, i2s up to 24-bit data ..................................................................................... ............. 18 figure 7. format 2, right ju stified 16-bit data. (available in control port mode only) format 3, right justified 24-bit da ta. (available in control port mode only) ............................................ 18 figure 8. i2c mode control port timing ....... ................................................................................. ............ 19 figure 9. spi control port timing ............................................................................................. ................ 20 figure 10. cs4270 typical connection diagram .................................................................................. .... 21 figure 11. de-emphasis curve .................................................................................................. ............... 27 figure 12. cs4270 recommended an alog input network ....................................................................... 28 figure 13. cs5344 exampl e analog input network ................................................................................ .. 29 figure 14. cs4270 recommended anal og output filter .......................................................................... 29 figure 15. suggested active-low mute circuit .................................................................................. ....... 30 figure 16. control port timing, spi mode ...................................................................................... .......... 31 figure 17. control port timing, i2c mode ...................................................................................... ........... 32 figure 18. de-emphasis curve .................................................................................................. ............... 38 figure 19. dac single-speed (fast) stopband rejection ......................................................................... 42 figure 20. dac single-speed (fast) transition ba nd ............................................................................ ... 42
ds686a1 5 cs4270 figure 21. dac single -speed (fast) transition band (detail) ................................................................... 42 figure 22. dac single-speed (fast) passband ripple ............................................................................ .42 figure 23. dac single -speed (slow) stopband rejection ........................................................................ 4 2 figure 24. dac single-s peed (slow) transition band ............................................................................ .. 42 figure 25. dac single-s peed (slow) transition band (detail) .. ................................................................ 4 3 figure 26. dac single -speed (slow) passband ripple ............................................................................ 43 figure 27. dac double-speed (fast) stopband rejection ........................................................................ 4 3 figure 28. dac double-speed (fast) transition band ............................................................................ .. 43 figure 29. dac double-speed (fast) tr ansition band (detail) .................................................................. 4 3 figure 30. dac double-speed (fast) passband ripple ............................................................................ 43 figure 31. dac double-speed (slow) stopband rejection ...................................................................... 44 figure 32. dac double-speed (slow) transition band ............................................................................ .44 figure 33. dac double-speed (s low) transition band (d etail) ................................................................. 44 figure 34. dac double-speed (slow) passband ripple ........................................................................... 4 4 figure 35. dac quad-speed (fast) stopband rejection .......................................................................... 4 4 figure 36. dac quad-speed (fast) transition band .............................................................................. ... 44 figure 37. dac quad-spe ed (fast) transition band (detail) ..................................................................... 45 figure 38. dac quad-speed (fast) passband ripple .............................................................................. .45 figure 39. dac quad-spe ed (slow) stopband rejection ......................................................................... 45 figure 40. dac quad-speed (slow) transition band .............................................................................. .45 figure 41. dac quad-spe ed (slow) transition band (detail) ...... ............................................................. 45 figure 42. dac quad-spe ed (slow) passband ripple ............................................................................. 4 5 figure 43. adc single -speed mode stopband rejection ........................................................................ 46 figure 44. adc single -speed mode transition band .................. ............................................................ .46 figure 45. adc single-s peed mode transition band (detail) ..... ............................................................. 46 figure 46. adc single -speed mode passband ripple ............................................................................. 4 6 figure 47. adc double-spee d mode stopband rejection ....................................................................... 46 figure 48. adc double-spee d mode transition band ............................................................................. 4 6 figure 49. adc double-speed mode transition band (detail) ................................................................. 47 figure 50. adc double-speed mode passband ripple ........................................................................... 47 figure 51. adc quad-s peed mode stopband rejection .......................................................................... 47 figure 52. adc quad-s peed mode transition band ................................................................................ 47 figure 53. adc quad -speed mode transition band (detail) ................................................................... 47 figure 54. adc quad-s peed mode passband ripple .............................................................................. 47 list of tables table 1. speed modes ........................................................................................................... ................... 22 table 2. clock ratios - stand-alone mode ....................................................................................... ........ 23 table 3. cs4270 stand-alone mode control....................................................................................... ..... 24 table 4. speed modes ........................................................................................................... ................... 25 table 5. clock ratios - control port mode.......... ............................................................................ .......... 25 table 6. analog input design pa rameters ........................................................................................ ........ 28 table 7. memory address pointer................................................................................................ ............. 32 table 8. functional mode selection............................................................................................. ............. 35 table 9. mclk divider configuration............................................................................................ ............ 35 table 10. dac digital interface formats ........................................................................................ .......... 36 table 11. adc digital interface formats ........................................................................................ .......... 36 table 12. soft cross or zero cr oss mode selection.............................................................................. ... 37 table 13. digital volume control ..................... .......................................................................... ............... 39
6 ds686a1 cs4270 1. pin descriptions - software mode pin name # pin description sdin 1 serial audio data input ( input ) - input for two?s complement serial audio data. lrck 2 left right clock ( input / output ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 3 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. sclk 4 serial clock ( input / output ) - serial clock for the serial audio interface. vd 5 digital power ( input ) - positive power supply for the digital section. dgnd 6 digital ground ( input ) - ground reference for the internal digital section. sdout 7 serial audio data output ( output ) - output for two?s complement serial audio data. vlc 8 control port power ( input ) - determines the signal level for the control port. sda/cdout 9 serial control data ( input / output ) - sda is a data i/o in i2c mode. cdout is the output data line for the control port interface in spi mode. scl/cclk 10 serial control port clock ( input ) - serial clock for the serial control port. ad0/cs 11 address bit 0 (i2c) / control port chip select (spi) (input) - ad0 is a chip address pin in i2c mode. cs is the chip select signal for spi format. ad1/cdin 12 address bit 1 (i2c) / serial control data ( input ) - ad1 is a chip address pin in i2c mode. cdin is the input data line for the control port interface in spi mode. ad2 13 address bit 2 (i2c) ( input ) - ad2 is a chip address pin in i2c mode. rst 14 reset ( input ) - the device enters a low power mode when low. aina ainb 15 16 analog input ( input ) - the full-scale analog input level is specified in the adc analog characteristics specification table. vq 17 quiescent voltage ( output ) - filter connection for internal quiescent voltage. filt+ 18 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. va 19 analog power ( input ) - positive power for the analog sections. agnd 20 analog ground ( input ) - ground reference. must be connected to analog ground. mutea muteb 21 24 mute control (output) - each pin is active during power-up in itialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. aouta aoutb 22 23 analog audio output ( output ) - the full-scale output level is specified in the dac analog character- istics specification table. 1 2 3 4 5 6 7 8 21 22 23 24 9 10 11 12 17 18 19 20 13 14 15 16 sdin lrck mclk sclk vd dgnd sdout vlc sda/cdout scl/cclk ad0/cs ad1/cdin muteb aoutb aouta mutea agnd va filt+ vq ainb aina rst ad2
ds686a1 7 cs4270 2. pin descriptions - stand-alone mode pin name # pin description sdin 1 serial audio data input ( input ) - input for two?s complement serial audio data. lrck 2 left right clock ( input / output ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 3 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. sclk 4 serial clock ( input / output ) - serial clock for the serial audio interface. vd 5 digital power ( input ) - positive power supply for the digital section. dgnd 6 digital ground ( input ) - ground reference for the internal digital section. sdout (m/s ) 7 serial audio data output ( output ) - output for two?s complement serial audio data. this pin must be pulled-up or pulled-down to select master or slave mode. vlc 8 control port power ( input ) - determines the signal level for the control port. m1 m0 9 10 mode selection ( input ) - determines the operational mode of the device. i2s /lj 11 serial audio interface select (input) - selects either the left-justified or i2s format for the serial audio interface. mdiv1 mdiv2 12 13 mclk divide ( input ) - configures mclk divider to divide by 1, 1.5, 2, or 4. rst 14 reset ( input ) - the device enters a low power mode when low. aina ainb 15 16 analog input ( input ) - the full-scale analog input level is specified in the adc analog characteristics specification table. vq 17 quiescent voltage ( output ) - filter connection for internal quiescent voltage. filt+ 18 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. va 19 analog power ( input ) - positive power for the analog sections. agnd 20 analog ground ( input ) - ground reference. must be connected to analog ground. mutea muteb 21 24 mute control (output) - each pin is active during power-up in itialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. aouta aoutb 22 23 analog audio output ( output ) - the full-scale output level is specified in the dac analog characteris- tics specification table. 1 2 3 4 5 6 7 8 21 22 23 24 9 10 11 12 17 18 19 20 13 14 15 16 sdin lrck mclk sclk vd dgnd sdout vlc m1 m0 i2s/lj mdiv1 muteb aoutb aouta mutea agnd va filt+ vq ainb aina rst mdiv2
8 ds686a1 cs4270 3. characteristics and specifications (all min/max characteristics and specifications are guaranteed over the specified operating conditions . typical performance characteristics and specifications are derive d from measurements taken at nominal supply voltages and t a = 25 c.) specified operating conditions (agnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (agnd = dgnd = 0 v, all voltage s with respect to ground.) ( note 1 ) notes: 1. operation beyond these limits may resu lt in permanent damage to the device. normal operation is not guaranteed at these extremes. 2. any pin except supplies. transient currents of up to 100 ma on t he analog input pins will not cause src latch-up. thermal characteristics 3. ja is specified according to jedec sp ecifications for multi-layer pcbs. parameters symbol min nom max units dc power supplies: analog digital control port interface va vd vlc 3.1 3.1 1.7 5.0 3.3 3.3 5.25 5.25 5.25 v v v ambient operating temperature (power applied) (-czz) (-dzz) t a-czz t a-dzz -10 -40 - - +70 +85 c c parameter symbol min typ max units dc power supplies: analog digital control port interface va vd vlc -0.3 -0.3 -0.3 - - - +6.0 +6.0 +6.0 v v v input current ( note 2 ) i in -10 - + 10 ma analog input voltage v in agnd-0.7 - va+0.7 v digital input voltage control port interface digital interface v ind-c v ind-d -0.3 -0.3 -vlc+0.3 vd+0.3 v v ambient operating temperature (power applied) t ac -50 - +95 c storage temperature t stg -65 - +150 c parameters symbol min typ max units allowable junction temperature - - 135 c junction to ambient thermal impedance (note 3) (multi-layer pcb) tssop (multi-layer pcb) soic (single-layer pcb) tssop (single-layer pcb) soic ja-tm ja-sm ja-ts ja-ss - - - - 70 60 105 80 - - - - c/w c/w c/w c/w
ds686a1 9 cs4270 dac analog characteris tics (CS4270-CZZ) (full-scale output sine wave, 997 hz (n ote 4), fs = 48/96/192 khz; test load r l = 3 k ? , c l = 10 pf (see figure 1 ). measurement bandwidth 10 hz to 20 khz, unless otherwise specified.) dac analog characteris tics (cs4270-dzz) (full-scale output sine wave, 997 hz (n ote 4), fs = 48/96/192 khz; test load r l = 3 k ? , c l = 10 pf (see figure 1 ). measurement bandwidth 10 hz to 20 khz, unless otherwise specified.) 4. one-half lsb of triangular pdf dither added to data. parameter va = 5v va = 3.3v min typ max min typ max unit dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 99 96 90 87 105 102 96 93 - - - - 97 94 90 87 103 100 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -95 -82 -42 -93 -73 -33 -89 -76 -36 -87 -67 -27 - - - - - - -95 -80 -40 -93 -73 -33 -89 -74 -34 -87 -67 -27 db db db db db db parameter va = 5v va = 3.3v min typ max min typ max unit dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 95 92 86 83 105 102 96 93 - - - - 93 90 86 83 103 100 96 93 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -95 -82 -42 -93 -73 -33 -85 -72 -32 -83 -63 -23 - - - - - - -95 -80 -40 -93 -73 -33 -85 -70 -30 -83 -63 -23 db db db db db db
10 ds686a1 cs4270 dac analog characteri stics - all modes parameter symbol min typ max unit interchannel isolation (1 khz) -100-db dc accuracy interchannel gain mismatch - 0.1 0.25 db gain drift -100 +100 ppm/c analog output full scale output voltage 0.640?va 0.688?va 0.739?va vpp max dc current draw from aouta or aoutb i outmax -10- a max ac-load resistance (see figure 2 ) r l -3-k ? max load capacitance (see figure 2 ) c l -100-pf output impedance of aouta and aoutb z out -100- ? aoutx agnd 3.3 f v out r l c l 100 50 75 25 2.5 51015 safe operating region capacitive load -- c (pf) l resistive load -- r (k ? ) l 125 3 20 figure 1. output test load figure 2. maximum loading
ds686a1 11 cs4270 dac combined interpol ation & on-chip anal og filter response (the filter characteristics have been normalized to the sample rate (fs) and can be referenced to the desired sam- ple rate by multiplying the give n characteristic by fs.) (see note 5 ) 5. amplitude vs. frequency plots of this data are available in section 11. ?appendix? on page 42 . see figures 19 through 42 . 6. response is clock depende nt and will scale with fs. 7. for single-speed mode, the measurem ent bandwidth is 0.5465 fs to 3 fs. for double-speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. for quad-speed mode, the measurement bandwidth is 0.7 fs to 1 fs. 8. de-emphasis is available only in single-speed mode. parameter symbol min typ max unit single-speed mode passband ( note 6 ) to -0.05 db corner to -3 db corner 0 0 - - .4780 .4996 fs fs frequency response 10 hz to 20 khz -.01 - +.08 db stopband .5465 - - fs stopband attenuation ( note 7 ) 50 - - db group delay tgd - 10/fs - s de-emphasis error (note 8) fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - +1.5/+0 +.05/-.25 -.2/-.4 db db db double-speed mode passband ( note 6 ) to -0.1 db corner to -3 db corner 0 0 - - .4650 .4982 fs fs frequency response 10 hz to 20 khz -.05 - +.2 db stopband .5770 - - fs stopband attenuation ( note 7 ) 55 - - db group delay tgd - 5/fs - s quad-speed mode passband ( note 6 ) to -0.1 db corner to -3 db corner 0 0 - - 0.397 0.476 fs fs frequency response 10 hz to 20 khz 0 - +0.00004 db stopband 0.7 - - fs stopband attenuation ( note 7 ) 51 - - db group delay tgd - 2.5/fs - s
12 ds686a1 cs4270 adc analog characteri stics (CS4270-CZZ) measurement bandwidth is 10 hz to 20 khz unless otherwise specified. input is 1 khz sine wave. 9. referred to the typical full-scale input voltage. parameter symbol va = 5v va = 3.3v min typ max min typ max unit single-speed mode fs = 48 khz dynamic range a-weighted unweighted 99 96 105 102 - - 96 93 102 99 - - db db total harmonic distortion + noise ( note 9 ) -1 db -20 db -60 db thd+n - - - -98 -82 -42 -92 - - - - - -95 -79 -39 -89 - - db db db double-speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 99 96 - 105 102 99 - - - 96 93 - 102 99 96 - - - db db db total harmonic distortion + noise ( note 9 ) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -82 -42 -95 -92 - - - - - - - -95 -79 -39 -87 -89 - - - db db db db quad-speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 99 96 - 105 102 99 - - - 96 93 - 102 99 96 - - - db db db total harmonic distortion + noise ( note 9 ) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -82 -42 -95 -92 - - - - - - - -95 -79 -39 -87 -89 - - - db db db db
ds686a1 13 cs4270 adc analog characteris tics (cs4270-dzz) measurement bandwidth is 10 hz to 20 khz unless ot herwise specified. input is 1 khz sine wave. 10. referred to the typical full-scale input voltage. parameter symbol va = 5v va = 3.3v min typ max min typ max unit single-speed mode fs = 48 khz dynamic range a-weighted unweighted 97 94 105 102 - - 94 91 102 99 - - db db total harmonic distortion + noise ( note 10 ) -1 db -20 db -60 db thd+n - - - -98 -82 -42 -90 - - - - - -95 -79 -39 -87 - - db db db double-speed mode fs = 96 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 97 94 - 105 102 99 - - - 94 91 - 102 99 96 - - - db db db total harmonic distortion + noise ( note 10 ) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -82 -42 -95 -90 - - - - - - - -95 -79 -39 -87 -87 - - - db db db db quad-speed mode fs = 192 khz dynamic range a-weighted unweighted 40 khz bandwidth unweighted 97 94 - 105 102 99 - - - 94 91 - 102 99 96 - - - db db db total harmonic distortion + noise ( note 10 ) -1 db -20 db -60 db 40 khz bandwidth -1 db thd+n - - - - -98 -82 -42 -95 -90 - - - - - - - -95 -79 -39 -87 -87 - - - db db db db
14 ds686a1 cs4270 adc analog characteri stics - all modes adc digital filter characteristics ( note 11 ) (measurement bandwidth is 10 hz to 20 khz unless otherwise specified) interchannel isolation -90-db dc accuracy interchannel gain mismatch -0.1-db gain error -3 - 3 % gain drift -100 - +100 ppm/c analog input characteristics full-scale input voltage 0.54*v a 0.56*va 0.58*v a vpp input impedance -300-k ? parameter symbol min typ max unit single-speed mode passband (-0.1 db) ( note 12 ) 0 - 0.47 fs passband ripple -0.1 - 0.035 db stopband ( note 12 ) 0.58 - - fs stopband attenuation -95 - - db group delay t gd -12/fs- s interchannel phase deviation - - 0.0001 deg double-speed mode passband (-0.1 db) ( note 12 ) 0 - 0.45 fs passband ripple -0.1 - 0.035 db stopband ( note 12 ) 0.68 - - fs stopband attenuation -92 - - db group delay t gd -9/fs- s interchannel phase deviation - - 0.0001 deg quad-speed mode passband (-0.1 db) ( note 12 ) 0 - 0.24 fs passband ripple -0.1 - 0.035 db stopband ( note 12 ) 0.78 - - fs stopband attenuation -97 - - db group delay t gd -5/fs- s interchannel phase deviation - - 0.0001 deg high-pass filter characteristics frequency response -3.0 db -0.13 db ( note 13 ) -1 20 - - hz hz phase deviation @ 20 hz ( note 13 ) -10-deg
ds686a1 15 cs4270 11. plots of this data are contained in section 11. ?appendix? on page 42 . see figures 43 through 54 . 12. the filter frequency resp onse scales precisely with fs. 13. response shown is for fs equal to 48 kh z. filter characteristics scale with fs. dc electrical characteristics (t a = 25 c; agnd=dgnd=0, all voltages with respec t to ground; mlck=12.288 mhz; master mode) 14. power down mode is defined as rst = low with all clocks and data lines held static. 15. valid with the recommended capacitor values on filt+ and vq as shown in the typical connection dia- gram. passband ripple --0db filter settling time 10 5 /fs s parameter symbol min typ max unit power supply power supply current va = 5 v (normal operation) va = 3.3 v vd, vlc = 5 v vd, vlc = 3.3 v i a i a i d i d - - - - 31 27 29 20 40 35 38 29 ma ma ma ma power supply current va = 5 v (power-down mode) ( note 14 ) vd, vlc = 5 v i a i d - - 1.51 0.45 - - ma ma power consumption va = 5 v, vd = vlc= 3.3 v normal operation va = 5 v, vd = vlc = 5 v normal operation power-down mode ( note 14 ) - - - - - - 221 255 9.8 296 - 323 mw mw mw power supply rejection ratio (1 khz) ( note 15 ) psrr - 60 - db common mode voltage nominal common mode voltage vq - va/2 - vdc maximum dc current source/sink from vq -1- a vq output impedance -25-k ? positive voltage reference filt+ nominal voltage filt+ - va - vdc maximum dc current source/sink from filt+ -10- a filt+ output impedance -18-k ? mute control mutea, muteb low-level output voltage -0-v mutea, muteb high-level output voltage -va-v maximum mutea & muteb drive current -3-ma parameter symbol min typ max unit
16 ds686a1 cs4270 digital characteristics 16. serial port signals include: sclk, lrck, sdout, sdin control port signals include: sda/ cdout, scl/cclk, ad1/cdin, ad0/cs , rst switching characteristic s - serial audio port (logic "0" = agnd = 0 v; logic "1" = vd, c l = 20 pf) parameter ( note 16 ) symbol min typ max units high-level input voltage serial port control port v ih 0.7xvd 0.7xvlc - - - - v v low-level input voltage serial port control port v il - - - - 0.2xvd 0.2xvlc v v high-level output voltage at i o = 2 ma serial port control port mutea, muteb v oh vd - 1.0 vlc - 1.0 va - 1.0 - - - - - - v v v low-level output voltage at i o = 2 ma v ol --0.4v input leakage current i in -10 - 10 a parameter symbol min typ max unit sample rate single-speed mode double-speed mode quad-speed mode fs fs fs 4 50 100 - - - 54 108 216 khz khz khz mclk specifications mclk frequency stand-alone mode ( note 17 ) control port mode f mclk f mclk 1.024 1.024 - - 55.296 55.296 mhz mhz mclk duty cycle 40 50 60 ns master mode lrck duty cycle -50-% sclk period --s sclk duty cycle -50-% sclk falling to lrck edge t slr -10 - 10 ns sclk falling to sdout valid t sdo - - 32 ns sdin valid to sclk rising setup time t sdis 16 - - ns sclk rising to sdin hold time t sdih 20 - - ns slave mode lrck duty cycle 40 50 60 % sclk period ( note 17 ) single-speed mode double-speed mode quad-speed mode t sclkw t sclkw t sclkw - - - - - - s s s sclk duty cycle 45 50 55 ns sclk falling to lrck edge t slr -10 - 10 ns 1 64 () fs ----------------- - 1 128 () fs -------------------- - 1 128 () fs -------------------- - 1 64 () fs ----------------- -
ds686a1 17 cs4270 17. in control port mode, mclk frequency and functional mode select bits must be configured according to table 5 , table 9 , and table 8 sclk falling to sdout valid t sdo - - 32 ns sdin valid to sclk rising setup time t sdis 16 - - ns sclk rising to sdin hold time t sdih 20 - - ns sdis t slr t sdout sclk output lrck output sdin sdo t sdih t sdis t slr t sdout sclk input lrck input sdin sdo t sdih t sclkw t figure 3. master mode serial audio port timing figure 4. slave mode serial audio port timing
18 ds686a1 cs4270 figure 5. format 0, left justified up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 figure 6. format 1, i2s up to 24-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 lrck sclk left channel sdata +5 +4 +3 +2 +1 lsb msb-1-2-3-4-5 32 clocks right channel lsb +5 +4 +3 +2 +1 lsb msb - 1 - 2 - 3 - 4 -5 +6 -6 +6 -6 figure 7. format 2, right justified 16-bit data. (available in control port mode only) format 3, right justified 24-bit data. (available in control port mode only)
ds686a1 19 cs4270 switching characteristics - i2c mode control port (inputs: logic 0 = dgnd, logic 1 = vlc) 18. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max unit i2c mode scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling ( note 18 ) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of both sda and scl lines t r -1s fall time of both sda and scl lines t f -300ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 8. i2c mode control port timing
20 ds686a1 cs4270 switching characteristics - spi control port (inputs: logic 0 = dgnd, logic 1 = vlc) 19. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 20. data must be held for sufficient time to bridge the transition time of cclk. 21. for f sck < 1 mhz parameter symbol min max unit spi mode cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling ( note 19 ) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 82 - ns cclk high time t sch 82 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time ( note 20 ) t dh 15 - ns rise time of cclk and cdin ( note 21 ) t r2 -100ns fall time of cclk and cdin ( note 21 ) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 9. spi control port timing
ds686a1 21 cs4270 4. typical conn ection diagram figure 10. cs4270 typical connection diagram ) lj (i2s/ cs / ad0 sda / cdin (m1) scl / cclk (m0) aina ainb rst power down and mode settings (control port) aouta mutea aoutb muteb analog conditioning & mute lrck sclk mclk timing logic & clock sdin ) s (m/ sdout audio data processor dgnd filt+ agnd vq vd va +3.3 v to 5 v +3.3 v to 5 v cs4270 2. gnd or vd 47 k ? 5.1 ? analog input network 47 f 0.1 f 1 f 0.1 f 1 f 0.1 f 1 f 0.1 f if using separate supplies for va and vd, 5.1 ? resistor not needed. see "grounding and power supply decoupling." vlc +1.8 v to 5 v 2. 1. 1. 1. 3. 3. 3. use pull-up resistors in software mode. in hardware mode, use pull-up or pull-down. see "mode selection & de-emphasis." 2 k ? 2 k ? (see figures 12 & 13) (see figures 14 & 15) use a 47 k ? pull-down to select master mode or 47 k ? pull-up to vd to select slave mode. see "master/slave mode selection." ad1 (mdiv2) ad2 (mdiv1)
22 ds686a1 cs4270 5. applications 5.1 stand-alone mode 5.1.1 recommended po wer-up sequence reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. it is also recomm ended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power glitch related issues. 5.1.2 master/slave mode the cs4270 supports operation in either master mode or slave mode. in master mode, lrck and sclk are outputs and are synchronously generated on-chip. lrck is equal to fs and sclk is equal to 64x fs. in slave mode, lrck and sclk are inputs, requiring external generation that is synchronous to mclk. it is recommended that sclk be 48x or 64x fs to maximize system performance. in stand-alone m ode, the cs4270 will enter slave mode when sdout (m/s ) is pulled low through a 47 k ? resistor. master mode may be accessed by placing a 47 k ? pull-up to vd on the sdout (m/s ) pin. configuration of clock ratios in each of these modes is outlined in table 2 . 5.1.3 system clocking the cs4270 will operate at sampling freq uencies from 4 khz to 216 khz. th is range is divided into three speed modes as shown in table 1 . mode sampling frequency single-speed 4-54 khz double-speed 50-108 khz quad-speed 100-216 khz table 1. speed modes
ds686a1 23 cs4270 5.1.4 clock ratio selection depending on whether the cs4270 is in master or slave mode, different mckl/lrck and sclk/lrck ratios may be used. these ratios are shown in the table 2 . 5.1.5 interpolation filter in stand-alone mode, the fast roll-off interpolation filt er is used. filter specifications can be found in sec- tion 3 . plots of the data are contained in section 11. ?appendix? on page 42 . 5.1.6 high-pass filter the operational amplifiers in the input circuitry dr iving the cs4270 may genera te a small dc offset into the adc. the cs4270 includes a high-pass filter after the decimator to remove any dc offset which could result in recording a dc level, poss ibly yielding "clicks" when switchi ng between devices in a multichannel system. in stand-alone mode, the high-pass filter cont inuously subtracts a measur e of the dc offset from the output of the decimation filter this fu nction cannot be disabled in stand-alone mode. master mode mclk/lrck sclk/lrck lrck mdiv2 mdiv1 single-speed 256 64 fs 0 0 384 64 fs 0 1 512 64 fs 1 0 1024 64 fs 1 1 double-speed 128 64 fs 0 0 192 64 fs 0 1 256 64 fs 1 0 512 64 fs 1 1 quad-speed 64 64 fs 0 0 96 64 fs 0 1 128 64 fs 1 0 256 64 fs 1 1 slave mode mclk/lrck sclk/lrck lrck mdiv2 mdiv1 single-speed 256 32, 48, 64, 128 fs 0 0 384 32, 48, 64, 96 fs 0 1 512 32, 48, 64, 128 fs 1 0 1024 32, 48, 64, 96 fs 1 1 double-speed 128 32, 48, 64 fs 0 0 192 32, 48, 64 fs 0 1 256 32, 48, 64 fs 1 0 512 32, 48, 64 fs 1 1 quad-speed 64 32, 48, 64 fs 0 0 96 32, 48, 64 fs 0 1 128 32, 48, 64 fs 1 0 256 32, 48, 64 fs 1 1 table 2. clock ratios - stand-alone mode
24 ds686a1 cs4270 5.1.7 mode selection & de-emphasis the sample rate, fs, can be adjusted from 4 khz to 216 khz and de-emphasis, optimized for 44.1 khz, is available in single-speed mode. in stand-alone ma ster mode, the cs4270 must be set to the proper mode via the mode pins, m1 and m0. in slave mode, the cs4270 auto-detects speed mode and the m0 pin becomes de-emphasis select. stand-alone de finitions of the mode pins are shown in table 3 . 5.1.8 serial audio inte rface format selection either i2s or left-justified serial audio data format may be selected in stand-alone mode. the selection will affect both the input and output format. placing a 10 k ? pull-up to vd on the i2s/lj pin will select the i2s format, while placing a 10 k ? pull-down to dgnd on the i2s/lj pin will select the left justified format. 5.2 control port mode 5.2.1 recommended power-up sequen ce - access to control port mode 1. pull rst low until the power supply, mclk, and lrck are stable. 2. release rst . the control port will be accessible. 3. initiate a spi or i2c transaction as described in section 6.1 or section 6.2 , respectively. 5.2.2 master / slave mode selection the cs4270 supports operation in either master mode or slave mode. in master mode, lrck and sclk are outputs and are synchronously generated on-chip. lrck is equal to fs and sclk is equal to 64x fs. in slave mode, lrck and sclk are inputs, requiring external generation that is synchronous to mclk. it is recommended that sclk be 48x or 64x fs to maximize system performance. configuration of cl ock ratios in each of thes e modes will be outlined in the table 10 and table 9 . in control port mode th e cs4270 will default to slave mode. the user may change this default setting by changing the status of the m/s bits in the functional control register (03h). mode 1 mode 0 mode sample rate (fs) de-emphasis 0 0 single-speed mode 4 khz - 54 khz off 0 1 single-speed mode 4 khz - 54 khz 44.1 khz 1 0 double-speed mode 50 khz - 108 khz off 1 1 quad-speed mode 100 khz - 216 khz off table 3. cs4270 stand-alone mode control
ds686a1 25 cs4270 5.2.3 system clocking the cs4270 will operate at sa mpling frequencies fr om 4 khz to 216 khz. this r ange is divided into three speed modes as shown in table 4 . 5.2.4 clock ratio selection in control port master mode, the user must config ure the mode bits (m0, m1, m2) to set the speed mode and select the appropriate clock ratios. depending on whether the cs4270 is in master or slave mode, different mclk/lrck and sclk/lrck ratios may be us ed. these ratios as well as the control port reg- ister bits are shown in table 5 , table 9 and section 8.3 on page 35 . mode sampling frequency single-speed 4-54 khz double-speed 50-108 khz quad-speed 100-216 khz table 4. speed modes master mode mclk/lrck sclk/lrck lrck mclk freq<2> mclk freq<1> mclk freq<0> single-speed 256 64 fs 0 0 0 384 64 fs 0 0 1 512 64 fs 0 1 0 768 64 fs 0 1 1 1024 64 fs 1 0 0 double-speed 128 64 fs 0 0 0 192 64 fs 0 0 1 256 64 fs 0 1 0 384 64 fs 0 1 1 512 64 fs 1 0 0 quad-speed 64 64 fs 0 0 0 96 64 fs 0 0 1 128 64 fs 0 1 0 192 64 fs 0 1 1 256 64 fs 1 0 0 slave mode mclk/lrck sclk/lrck lrck mclk freq<2> mclk freq<1> mclk freq<0> single-speed 256 32, 64, 128 fs 0 0 0 384 32, 48, 64, 96, 128 fs 0 0 1 512 32, 64, 128 fs 0 1 0 768 32, 48, 64, 96, 128 fs 0 1 1 1024 32, 64, 128 fs 1 0 0 table 5. clock ratios - control port mode
26 ds686a1 cs4270 5.2.5 internal digital loopback in control port mode, the cs4270 supports an internal digital loopback mode in which the output of the adc is routed to the input of the dac. this mode may be activated by setting the digital loopback bit in the adc & dac ctrl register (04h). when this bit is set, the status of the dac_dif(4:3) bits in register 04h will be disregarded by the cs4270. any changes made to the dac_dif(4:3) bits while the digital loopback bit is set will have no impact on operation until the digital loopback bit is released, at which time the digital interface format of the dac will operate according to the format se lected in the dac_dif(4:3) bits. while the digital loopback bit is set, data will be present on the sdout pin in the format selected in the adc_dif( 0) bit in register 04h. 5.2.6 auto-mute the auto-mute function is controlled by the status of the auto mute bit in the mute register. when set, the dac output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-static data will rele ase the mute. detection and muti ng are done indep endently for each channel. the common mo de on the output will be retained and th e mute control pin for that channel will become active during the mute period. the muting functi on is affected, similar to volume control changes, by the soft and zerocross bits in the transition and co ntrol register. the auto mute bit is set by default. 5.2.7 high-pass filter a nd dc offset calibration the input circuitry driving the cs4270 may generate a small dc offset into the a/d converter. the cs4270 includes a high-pass filter after the decimator to remo ve any dc offset which could result in recording a dc level, possibly yielding "clicks" when switch ing between devices in a multichannel system. the high-pass filter continuously subtracts a measure of the dc offset from the output of the decimation filter. the high-pass filter can be e nabled if the hpf_freeze bit is set during normal operation, the current value of the dc offset for the corr esponding channel is frozen and this dc offset will continue to be sub- tracted from the conversion result. this feature makes it possible to perform a system dc offset calibration by: 1. running the cs4270 with the high-pass filter enabled until the filter settles. see the digital filter characteristics for filter settling time. 2. disabling the high-pass filter and freezing the stored dc offset. a system calibration performed in th is way will eliminate offsets anywher e in the signal path between the calibration point and the cs4270. double-speed 128 32, 48, 64 fs 0 0 0 192 32, 48, 64 fs 0 0 1 256 32, 48, 64 fs 0 1 0 384 32, 48, 64 fs 0 1 1 512 32, 64 fs 1 0 0 quad-speed 64 32 fs 0 0 0 96 48, 64 fs 0 0 1 128 32, 64 fs 0 1 0 192 48, 64 fs 0 1 1 256 32, 64 fs 1 0 0 master mode table 5. clock ratios - cont rol port mode (continued)
ds686a1 27 cs4270 5.2.8 de-emphasis one de-emphasis mode is available via the control port and is optimized for 44.1 khz sampling rate. 5.2.9 oversampling modes the cs4270 operates in one of three oversampling modes based on the input sample rate. mode selec- tion is determined by the fm_&_m/s_mode[1:0] bits in the functional mode register (03h). single-speed mode supports input sample rates up to 54 khz an d uses a 128x oversampling ratio. double-speed mode supports input sample rates up to 108 khz and uses an oversampling ratio of 64x. quad-speed mode supports input sample rates up to 216 khz and uses an oversampling ratio of 32x. see table 10 for con- trol port mode settings. 5.3 de-emphasis filter the cs4270 includes on-chip digital de-emphasis. figure 11 shows the de-emphasis curve for fs equal to 44.1 khz. the frequ ency response of the de-emphasis curv e will scale proportio nally with changes in sample rate, fs. please see section 5.1.7 for the desired de-emphasis control for stand-alone mode and section 5.2.8 for control port mode. the de-emphasis featur e is included to ac commodate audio re cordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. de-emphasis is only available in single-speed mode. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 11. de-emphasis curve
28 ds686a1 cs4270 5.4 analog connections 5.4.1 input connections the analog modulator samples th e input at 6.144 mhz.the digi tal filter will reject signal s within the stopband of the filter. however, there is no reject ion for input signals which are multiples of the input sampling frequency (n 6.144 mhz), where n=0,1,2,... refer to figure 12 which shows the recommended to pology of the analog input network. the capacitor values chosen not only provide the appropriate filtering of noise at the modulator sampling frequency, but also act as a charge s ource for the internal sampling circuits. the use of capacitors which have a large voltage coefficient (such as general purpose cera mics) must be avoided since these can degrade signal lin- earity. three parameters determine the values of resistors r1 and r2 as shown in figure 12 : source impedance, attenuation, and input impedance. source impedance is defined as the impedance as seen from the adc looking back into the signal network. analog perfor mance is optimized for sma ll source impedance and a source impedance above 2.5 k ? results in degraded thd+n. the required attenuation factor depends on the magnit ude of the input signal. the full-scale input voltage scales with va; for va = 5 v, the cs5344 full-scale inpu t magnitude is 1 vrms. r1 and r2 should be set such that an input signal greater than the full-scale input should be attenuated to the appropriate magni- tude. typical line-level voltage in aud io applications is 2 vrms, in whic h case r1 and r2 must combine to form an attenuation factor of 2, thus giving the cs5344 a 1 vrms input. input impedance is the impedance from the signal sour ce to the adc analog input pins. the target input impedance depends on the overall system specifications, but typica l audio systems requ ire an input im- pedance of 10 k ? . table 6 shows the input parameters and the associated design equations. figure 13 illustrates an example configurati on for a source impedance of 46 ? , an attenuation factor of 1, and input impedance of 9.8 k ?. source impedance attenuation factor input impedance table 6. analog input design parameters figure 12. cs4270 recommended analog input network cs4270 ainx 2200 pf r2 10 f r1 analog input r 1 r 2 () r 1 r 2 + ------------------------ - r 2 r 1 r 2 ------------------- - r 1 r 2 + ()
ds686a1 29 cs4270 5.4.2 output connections the analog output filter present in the cs4270 is a sw itched-capacitor filter fo llowed by a continuous time low pass filter. its response, combined with that of the digital interpolator, is given in figures figures 19 - 42 . the recommended external analog circuitry is shown in figure 14 . 5.5 mute control the mute control pins become active during power- up initialization, reset, muting, when the mclk to lrck ratio is incorrect, and during power-down. the mute pins are intended to be used as control for an external mute circuit in orde r to add off-chip mute capability. the cs4270 also features auto-mute, which is enabled by default. the auto-mute function causes the mute pin corresponding to an individual channel to activate following the reception of 8192 consecutive static-level audio samples on the re spective channel. a single transiti on of data on the channel will cause the corresponding mute pin to deactivate. use of the mute control function is not mandator y but recommended for designs requiring the absolute minimum in extraneous clicks an d pops. also, use of the mute c ontrol function can enable the system figure 13. cs5344 example analog input network cs4270 ainx 2200 pf 9.76 k ? 10 f 47 ? analog input figure 14. cs4270 recommended analog output filter analog output r + 470 c= 4 f s ( r470) 3.3 f 10k ? c 470 ? + r ext ext ext for best 20 khz response aoutx cs4270
30 ds686a1 cs4270 designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. the mute pins are active-low. see figure 15 for a suggested active-low mute circuit. 5.6 synchronization of multiple devices in systems where mult iple adcs are required, ca re must be taken to achiev e simultaneous sampling. to ensure synchronous sampling, the mclk and lrck must be the same for all of the cs4270?s in the sys- tem. if only one mclk source is needed, one solution is to place one cs4270 in master mode, and slave all of the other cs4270?s to the one master. if mu ltiple mclk sources are needed, a possible solution would be to supply all clocks from the same external source and time the cs4270 reset with the inactive edge of mclk. this will ensure that all conver ters begin sampling on the same clock edge. 5.7 grounding and power supply decoupling as with any high resolution converter, the cs4270 requ ires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 10 shows the recommended power arrangements, with va and vd connected to clean su pplies. vd, which powers the digital filter, may be run from the system digital supply (vd) or may be powered from the analog supply (va) via a resistor. in this case, no additional devices should be powered from vd. power supply decoupling capacitors should be as near to the cs4270 as possible, with the low value ceramic capacitor being the nearest. all signals, especially clocks, should be kept away from the vr ef and vcom pins in order to avoid unwanted cou- pling into the modulators. the vref and vcom deco upling capacitors, particul arly the 0.1 f, must be positioned to minimize the electrical path from vref and agnd. the cdb4270 evaluation board dem- onstrates the optimum layout and power supply arrangements. to minimize digital noise, connect the cs4270 digital outputs only to cmos inputs. lpf +v ee -v ee 560 ? audio out 2 k ? 10 k ? -v ee +v a mmun2111lt1 aoutx mutex cs4270 ac couple 47 k ? figure 15. suggested active-low mute circuit
ds686a1 31 cs4270 6. control port interface the control port is used to load all the internal settings of the cs4270. the operation of the control port may be completely asynchronous to the audio sample rate. howeve r, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port has 2 modes: spi and i2c, with the cs4 270 operating as a slave to control messages in both modes. if i2c operation is desired, ad0/cs should be tied to vlc or dgnd. if the cs4270 ever detects a high to low transition on ad0/cs after power-up, spi mode will be selected. upon release of the rst pin, the cs4270 will wait approx imately 10 ms before it begin s its start-up sequence. the part defaults to stand-alone mode, in which all operational modes are controlled as described in section 5.1 on page 22 . if the user initiates communication to the part through the spi or i2c interface, the part enters control-port mode and all operational modes are controlled by the contro l port registers. if system requirements do not allow writing to the control port immediately following the release of rst , the sdin line should be held at logic ?0? until the proper serial mode can be selected. 6.1 spi ? mode in spi mode, cs is the cs4270 chip select signal, cclk is the control port bit clock, cdin is the input data line from the microcontroller and the chip address is 1001111. all control signals are inputs and data is clocked in on the rising edge of cclk. figure 16 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first 7 bits on cdin form the chip address, and must be 1001111. the eighth bit is a read/write indicator (r/w ), which must be low to write. the next 8 bits form the memory address pointer (map), which is set to the address of the regist er that is to be update d. the next 8 bits are the data wh ich will be placed into the register designated by the map. see table 9 on page 35 . the cs4270 has map auto increment capability, enabled by the incr bit in the map. if incr is 0, then the map will stay constant for successive writes. if incr is set, then m ap will auto increment after each byte is written, allowing block wr ites to successive registers. map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 1001111 figure 16. control port timing, spi mode
32 ds686a1 cs4270 6.2 i2c mode in i2c mode, sda is a bi-directional data line. data is clocked into and out of the part by the clock, scl, with the clock to data rela tionship as shown in figure 17 . there is no cs pin. pins ad0, ad1, and ad2 form the partial chip address and should be tied to vlc or dg nd as required. the upper 4 bits of the 7-bit address field must be 1001. to communicate with the cs4270, the three lower bits of the chip address field should match the setting on the ad0, ad1, and ad2 pins. the eighth bit of the address byte is the r/w bit (high for a read, low for a write). the next byte is the memory address pointer, map, which selects the register to be read or written. if the operation is a write, the map is then followed by t he data to be written. if the operation is a read, then the contents of the register pointed to by the map will be output after th e chip address. the cs4270 has map auto increment capa bility, enabled by the incr bit in the map. if incr is 0, then the map will stay constant for successive writes. if incr is set, then map will auto increment after each byte is written, allowing block reads or writes of successive registers. 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000 incr - auto map increment enable default = ?0?. 0 - disabled 1 - enabled map(3:0) - memory address pointer default = ?0000?. table 7. memory address pointer sda scl 1001 addr ad2 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 ad0 - figure 17. control port timing, i2c mode
ds686a1 33 cs4270 7. register qu ick reference this table shows the register names and their associat ed default values. addr function 7 6 5 4 3 2 1 0 01h id id<3> id<2> id<1> id<0> rev<3> rev<2> rev<1> rev<0> 11 0 0 0 0 0 1 02h power control freeze reserved pdn_adc reserved reserved reserved pdn_dac pdn 00 0 0 0 0 0 0 03h funct mode reserved reserved fm_&_m/s _mode1 fm_&_m/s_ mode0 mclk freq<2> mclk freq<1> mclk freq<0> popguard disable 00 1 1 0 0 0 0 04h serial format adc hpf freeze a adc hpf freeze b digital loopback dac_dif1 dac_dif0 reserved reserved adc_dif0 00 0 0 0 0 0 0 05h transition control dac single vol soft_dac zc_dac invert adc ch b invert adc ch a invert dac ch b invert dac ch a de-emph 01 1 0 0 0 0 0 06h mute reserved reserved auto mute mute adc sp ch b mute adc sp ch a mute polarity mute dac ch b mute dac ch a 00 1 0 0 0 0 0 07h vol ctrl aouta daca vol<7> daca vol<6> daca vol<5> daca vol<4> daca vol<3> daca vol<2> daca vol<1> daca vol<0> 00 0 0 0 0 0 0 08h vol ctrl aoutb dacb vol<7> dacb vol<6> dacb vol<5> dacb vol<4> dacb vol<3> dacb vol<2> dacb vol<1> dacb vol<0> 00 0 0 0 0 0 0
34 ds686a1 cs4270 8. register description ** all registers are read/write in i2c mode and spi mode, unless otherwise noted** 8.1 chip id - address 01h function: this register is read-only. bits 7 through 4 are the part number id which is 1100b (01h) and the remaining bits (b3:b0) are for the chip revision. 8.2 power control - address 02h 8.2.1 freeze (bit 7) function: this function allows modifications to be made to certain control port bi ts without the changes taking effect until the freeze bit is disabled. to make multiple chang es to these bits take effect simultaneously, set the freeze bit, make all changes, then clear the freeze bit. the bits affected by the freeze function are listed below: ? register 05h (bits 7:0) ? register 06h (bits 7:0) ? register 07h (bits 7:0) ? register 08h (bits 7:0) 8.2.2 pdn_adc (bit 5) function: the adc portion of the device will enter a low-power state whenever this bit is set. 8.2.3 pdn_dac (bit 1) function: the dac portion of the device will enter a low-power state whenever this bit is set. 8.2.4 power down (bit 0) function: the device will enter a low-power stat e whenever this bit is set. the contents of th e control registers are retained when the device is in power-down. 76543210 id<3> id<2> id<1> id<0> rev<3> rev<2> rev<1> rev<0> 76543210 freeze reserved pdn_adc reserved reserved reserved pdn_dac pdn
ds686a1 35 cs4270 8.3 mode control - address 03h 8.3.1 adc functional mode & ma ster / slave mode (bits 5:4) function: in control port master mode, the user must config ure the cs4270 speed mode with these bits. in control port slave mode, the cs4270 auto-detects speed mode. 8.3.2 ratio select (bits 3:1) function: these bits are used to select the clocking ratios. 8.3.3 popguard disable (bit 0) function: disables popguard when set. po pguard is enabled by default. 8.4 adc and dac control - address 04h 8.4.1 adc hpf freeze a (bit 7) function: when this bit is set, the internal high-pass filter for th e selected channel will be disabled.the current dc offset value will be frozen and continuously subtracted from the conversion result. section 5.2.7 ?high- pass filter and dc offset calibration? on page 26 . 76543210 reserved reserved fm_&_m/s_ mode1 fm_&_m/s_ mode0 mclk freq<2> mclk freq<1> mclk freq<0> popguard disable fm_&_m/s_ mode1 fm_&_m/s_ mode0 mode 00 single-speed mode: 4 to 54 khz sample rates 01 double-speed mode: 50 to 108 khz sample rates 10 quad-speed mode: 100 to 216 khz sample rates 11 slave mode (default) table 8. functional mode selection mclk freq<2> mclk freq<1> mclk freq<0> mode 00 0 divide by 1 (default) 00 1 divide by 1.5 01 0 divide by 2 01 1 divide by 3 10 0 divide by 4 table 9. mclk divider configuration 76543210 adc hpf freeze a adc hpf freeze b digital loopback dac_dif1 dac_dif0 reserved reserved adc_dif0
36 ds686a1 cs4270 8.4.2 adc hpf freeze b (bit 6) function: when this bit is set, the internal high-pass filter for the selected channel will be disabled.the current dc offset value will be frozen an d continuously subtracted fr om the conversion result. section 5.2.7 ?high- pass filter and dc offset calibration? on page 26 . 8.4.3 digital loopback (bit 5) function: when this bit is set, an internal digital loopback from the adc to the dac will be enabled. please refer to section 5.2.5 ?internal digital loopback? on page 26 . 8.4.4 dac digital interface format (bits 4:3) function: the dac digital interface format and the options are detailed in table 10 and figures 5 through 7 . 8.4.5 adc digital interface format (bit 0) function: the required relationship between lrck, sclk an d sdout for the adc is defined by the adc digital interface format. the options are detailed in table 11 and may be seen in figures 5 and 6 . dac_dif1 dac_dif0 desc ription format figure 0 0 left justified, up to 24-bit data (default) 0 5 0 1 i2s, up to 24-bit data 1 6 1 0 right justified, 16-bit data 2 7 1 1 right justified, 24-bit data 3 7 table 10. dac digital interface formats adc_dif description format figure 0 left justified, up to 24-bit data (default) 0 5 1 i2s, up to 24-bit data 1 6 table 11. adc digital interface formats
ds686a1 37 cs4270 8.5 transition control - address 05h 8.5.1 dac single volume (bit 7) function: the aouta and aoutb volume levels are independen tly controlled by the a and the b channel volume control bytes when this function is disabled. the volume on both aouta and aoutb are determined by the a channel volume control byte (07h) and the b c hannel byte (08h) is ignored when this function is enabled. volume and muting functions are affected by the soft ramp and zerocross functions below. 8.5.2 soft ramp or zero cross enable (bits 6:5) function: soft ramp enable soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. see table 12 on page 37 . zero cross enable zero cross enable dict ates that signal level cha nges, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a time- out period between 512 and 1024 sample periods (10. 7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. see table 9 on page 35 . soft ramp and zero cross enable soft ramp and zero cross enable dictate that signal le vel changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and be implemented on a signal zero crossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sam- ple rate) if the signal does not encounter a zero crossing. the zero cross f unction is independently mon- itored and implemented for each channel. see table 9 on page 35 . 8.5.3 invert signal polarity (bits 4:1) function: when set, this bit activates an inversion of the signal polarity for the appropriate channel. this is useful if a board layout error has occurred or in other situations where a 180 degree phase shift is desirable. 76543210 dac single volume soft_dac zc_dac invert adc ch b invert adc ch a invert dac ch b invert dac ch a de-emph soft zerocross mode 0 0 changes to affect immediately 0 1 zero cross enabled 1 0 soft ramp enabled 1 1 soft ramp and zero cross enabled (default) table 12. soft cross or zero cross mode selection
38 ds686a1 cs4270 8.5.4 de-emphasis control (bit 0) function: implementation of the standard 50/15 s digital de-emphasis filter on the dac output requires reconfigu- ration of the digital filter to maintain the proper filter response for 44.1 khz sample rate. figure 18 shows the filter response. note: de-emphasis is available only in single-speed mode. 8.6 mute control - address 06h 8.6.1 auto-mute (bit 5) function: when set, enables the auto-mute function. section 5.2.6 ?auto-mute? on page 26 . 8.6.2 adc channel a & b mute (bits 4:3) function: when this bit is set, the output of th e adc for the selected channel will be muted. 8.6.3 mute polarity (bit 2) function: the mutea and muteb pins (pins 24 and 21) are active low by default. when this bit is set, these pins are active high. 8.6.4 dac channel a & b mute (bits 1:0) function: when this bit is set, the output of th e dac for the selected channel will be muted. 76543210 auto mute mute adc sp ch b mute adc sp ch a mute polarity mute dac sp ch b mute dac sp ch b gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 18. de-emphasis curve
ds686a1 39 cs4270 8.7 dac channel a volume control - address 07h function: see section 8.8 dac channel b vo lume control - address 08h . 8.8 dac channel b volume control - address 08h function: the digital volume control a llows the user to attenuate the signal in 0.5 db increments from 0 to -127 db. the vol<0> bit activates a 0.5 db attenuation when set, and no attenuation when cleared. the vol[7:1] bits activate attenuation equal to their decimal value (in db). example volume settings are decoded as shown in table 13 . the volume changes are implemented as dictated by the dacsoft and daczero- cross bits in the transition control register (see section 8.5.2 ). 76543210 daca vol<7> daca vol<6> daca vol<5> daca vol<4> daca vol<3> daca vol<2> daca vol<1> daca vol<0> 76543210 dacb vol<7> dacb vol<6> dacb vol<5> dacb vol<4> dacb vol<3> dacb vol<2> dacb vol<1> dacb vol<0> binary code volume setting 00000000 0 db 00000001 -0.5 db 00101000 -20 db 00101001 -20.5 db 11111110 -127 db 11111111 -127.5 db table 13. digital volume control
40 ds686a1 cs4270 9. parameter definitions dynamic range the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement ov er the specified bandwidth made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the me asurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering society, aes17- 1991, and the electronic industries association of ja- pan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right channe ls. measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left an d right channels. units in decibels. gain error the deviation from the nominal full-scale a nalog output for a full-scale digital input. gain drift the change in gain value with te mperature. units in ppm/c. offset error the deviation of the mid-scale transition (111...111 to 000...000) from the ideal. units in mv.
ds686a1 41 cs4270 10.package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mis- match and are measured at the parting line, mold flas h or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/intr usion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimen- sion ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a----0.47----1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2 , 3 d 0.378 bsc 0.382 bsc 0.386 bsc 9.60 bsc 9.70 bsc 9.80 bsc 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.029 0.50 0.60 0.75 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 24l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
42 ds686a1 cs4270 11.appendix 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 19. dac single-speed (fast) stopband rejection figure 20. dac single-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 21. dac single-speed (fast) transition band (detail) figure 22. dac single-speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 23. dac single-speed (slow) stopband rejection figure 24. dac single-speed (slow) transition band
ds686a1 43 cs4270 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) figure 25. dac single-speed (slow) transition band (detail) figure 26. dac single-speed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 27. dac double-speed (fast) stopband rejection figure 28. dac double-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 29. dac double-speed (fast) transition band (detail) figure 30. dac double-speed (fast) passband ripple
44 ds686a1 cs4270 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 31. dac double-speed (slow) stopband rejection figure 32. dac double-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.3 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 33. dac double-speed (slow) transition band (detail) figure 34. dac double-speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 35. dac quad-speed (fast) stopband rejection figure 36. dac quad-speed (fast) transition band
ds686a1 45 cs4270 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 37. dac quad-speed (fast) transition band (detail) figure 38. dac quad-speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 39. dac quad-speed (slow) stopband rejection figure 40. dac quad-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.1 2 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 41. dac quad-speed (slow) transition band (detail) figure 42. dac quad-speed (slow) passband ripple
46 ds686a1 cs4270 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 frequency (normalized to fs) amplitude (db) figure 43. adc single-speed mode stopband rejection figure 44. adc single-speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 45. adc single-speed mode transition band (detail) figure 46. adc single-speed mode passband ripple -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70 frequency (normalized to fs) amplitude (db) figure 47. adc double-speed mode stopband rejection figure 48. adc double-speed mode transition band
ds686a1 47 cs4270 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.40 0.43 0.45 0.48 0.50 0.53 0.55 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 frequency (normalized to fs) amplitude (db) figure 49. adc double-speed mode transition band (detail) figure 50. adc double-speed mode passband ripple -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00.10.20.30.40.50.60.70.80.91.0 frequency (normalized to fs) amplitude (db) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 frequency (normalized to fs) amplitude (db) figure 51. adc quad-speed mode stopband rejection figure 52. adc quad-speed mode transition band -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 frequency (normalized to fs) amplitude (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.00 0.05 0.10 0.15 0.20 0.25 frequency (normalized to fs) amplitude (db) figure 53. adc quad-speed mode transition band (detail) figure 54. adc quad-speed mode passband ripple
48 ds686a1 cs4270 12.revision history release date changes a1 may 2005 initial advance release contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice "advance" product information desc ribes products that are in development and subjec t to development changes. cirrus logic, inc . and its subsidiaries ("cirrus") believe that the information contained in this document is accu rate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant informati on to verify, before placing orders, that information being relied on is current and complete. all products ar e sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limi tation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no licens e, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus ow ns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or prom otional purposes, or for creating any work for resale. certain applications using semi conductor products may involve po tential risks of death, pers onal injury, or severe prop- erty or environmental damage (?critical applications?). cir rus products are not designed, au thorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security de- vices, life support products or other critical applications. inclusion of cirrus products in such applications is under- stood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchant ability and fitness for particular purpo se, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or perm its the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc.

▲Up To Search▲

Price & Availability of CS4270-CZZ

	To Download CS4270-CZZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .